| CPC H01L 23/564 (2013.01) [H01L 22/32 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01)] | 25 Claims |
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25. A semiconductor wafer comprising:
at least four chip regions disposed in a substrate;
at least four chip sealing regions corresponding to said at least four chip regions, wherein each of the at least four chip sealing regions surrounds a corresponding one of the at least four chip regions;
a scribe lane region surrounding all of the at least four chip sealing regions and filling a space between the at least four chip sealing regions; and
test circuit patterns positioned laterally each of said at least four chip regions in the scribe lane region,
wherein the semiconductor wafer further comprising:
integrated circuits in the at least four chip regions;
first chip guards in the at least four chip sealing regions, the first chip guards being directly connected to first ground wells formed in the at least four chip sealing regions; and
second chip guards in the scribe lane region,
wherein the test circuit patterns are disposed to be laterally spaced apart from the second chip guards,
wherein the test circuit patterns include ground lines electrically connected to second ground wells formed in the scribe lane region,
wherein the second chip guards include ground wiring layers that are laterally extended and are electrically connected to the ground lines of the test circuit patterns,
wherein the second chip guards are electrically connected to second ground wells of the substrate via the ground wiring layers and the ground lines, without direct electrical paths from the second chip guards to the substrate for electrically grounding the second chip guards.
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