| CPC H01L 23/544 (2013.01) [H01L 21/4846 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/562 (2013.01); H01L 25/105 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/92125 (2013.01)] | 20 Claims |

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1. A semiconductor package comprising:
an interposer comprising an upper pad and an upper passivation layer partially covering the upper pad;
a semiconductor chip disposed on the interposer;
a conductor pattern disposed on the interposer and contacting the upper pad;
a first guide pattern disposed on the interposer, the first guide pattern comprising a main opening and at least one sub-opening connected to the main opening;
a first support disposed on the interposer, the first support comprising a core portion and a peripheral portion surrounding the core portion, and a lower surface of the first support being disposed in the main opening of the first guide pattern;
an upper redistribution structure disposed on the semiconductor chip and contacting the conductor pattern and the first guide pattern; and
an encapsulant between the interposer and the upper redistribution structure,
wherein the encapsulant contacts an inner wall of the main opening, an inner wall of the at least one sub-opening and a side surface of the first support.
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