US 12,451,431 B2
Stacked semiconductor devices with topside and backside interconnect wiring
Tao Li, Slingerlands, NY (US); Liqiao Qin, Albany, NY (US); Mukta Ghate Farooq, Hopewell Jct, NY (US); Ruilong Xie, Niskayuna, NY (US); and Kisik Choi, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on May 2, 2022, as Appl. No. 17/661,583.
Prior Publication US 2023/0352406 A1, Nov. 2, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 23/481 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06541 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first semiconductor device on a substrate;
a first interconnect wiring structure over the first semiconductor device;
a second interconnect wiring structure under a second semiconductor device, wherein the second interconnect wiring structure physically contacts the first interconnect wiring structure;
a third interconnect wiring structure (i) on the second semiconductor device and (ii) electrically contacting the second semiconductor device through a top surface of the second semiconductor device; and
a first through-silicon via from a bottom surface of the substrate to a top surface of the first interconnect wiring structure, wherein the first through-silicon via is tapered such that a width of a bottom surface of the first through-silicon via is greater than a width of a top surface of the first through-silicon via.