US 12,451,430 B2
Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby
Chung-Hui Chen, Hsinchu (TW); Cheng-Hsiang Hsieh, Hsinchu (TW); Wan-Te Chen, Hsinchu (TW); Tzu Ching Chang, Hsinchu (TW); Wei Chih Chen, Hsinchu (TW); Ruey-Bin Sheen, Hsinchu (TW); and Chin-Ming Fu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 9, 2021, as Appl. No. 17/196,240.
Claims priority of provisional application 63/031,409, filed on May 28, 2020.
Prior Publication US 2021/0375762 A1, Dec. 2, 2021
Int. Cl. H01L 23/528 (2006.01); G06F 30/392 (2020.01); G06F 30/3953 (2020.01); G06F 30/398 (2020.01)
CPC H01L 23/5286 (2013.01) [G06F 30/392 (2020.01); G06F 30/3953 (2020.01); G06F 30/398 (2020.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device based on a dual-architecture-compatible design, the method comprising:
forming one or more components of one or more transistors in a transistor (TR) layer of the semiconductor device; and
performing one of:
(A) fabricating additional components according to a buried power rail (BPR) architecture for the semiconductor device, the BPR architecture including layers below the transistor layer (sub-TR layers) and layers over the transistor layer (supra-TR layers); or
(B) fabricating additional components according to a non-buried power rail (non-BPR) architecture for the semiconductor device, the non-BPR architecture including supra-TR layers; and
wherein:
the dual-architecture-compatible design is substantially equally suitable either to adaptation into the BPR architecture or adaptation into the non-BPR architecture;
the (A) fabricating additional components according to a BPR architecture includes:
in corresponding sub-TR layers, forming various non-dummy structures (non-dummy sub-TR structures) correspondingly coupled to one or more of the one or more components of the one or more transistors; and
in corresponding supra-TR layers, forming various dummy structures (dummy supra-TR structures) which are corresponding artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the non-BPR architecture; and
the (B) fabricating additional components according to a non-BPR architecture includes:
in corresponding supra-TR layers:
forming various non-dummy structures (non-dummy supra-TR structures) correspondingly coupled to one or more of the one or more components of the one or more transistors; and
forming various dummy structures (dummy supra-TR structures) which are corresponding artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR architecture.