US 12,451,429 B2
Interconnection structure for a semiconductor device
Zheng Tao, Heverlee (BE); and Stefan Decoster, Bertem (BE)
Assigned to IMEC VZW, Leuven (BE)
Filed by IMEC VZW, Leuven (BE)
Filed on Nov. 8, 2022, as Appl. No. 18/053,636.
Claims priority of application No. 21210946 (EP), filed on Nov. 29, 2021.
Prior Publication US 2023/0170300 A1, Jun. 1, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 21/32139 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76885 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for forming an interconnection structure for a semiconductor device, the method comprising:
forming a conductive layer on an insulating layer;
etching the conductive layer to form a first conductive line, using a first mask layer as an etch mask;
forming a spacer on a side wall of a first end portion of the first conductive line;
forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer, such that the first and the second conductive lines are extending along the same line and separated by the spacer;
forming a recess in the second conductive line, the recess extending along a portion of the second conductive line; and
forming a second mask layer in the recess.