| CPC H01L 23/528 (2013.01) [H10D 84/0149 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
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1. An integrated circuit comprising:
an active region extending in a first direction;
a plurality of gate electrodes extending in a second direction in parallel with each other, the second direction being perpendicular to the first direction;
a plurality of source/drain regions provided on the active region between the plurality of gate electrodes;
a first gate contact connected to the plurality of gate electrodes and extending in the first direction;
a plurality of first gate wiring patterns provided in a first wiring layer, wherein each of the plurality of first gate wiring patterns are electrically connected to each of the plurality of gate electrodes through the first gate contact, wherein the plurality of first gate wiring patterns are spaced apart from each other along the first direction, wherein the plurality of first gate wiring patterns extend farther in the second direction than the first gate contact extends in the second direction, and wherein the first gate contact extends between the plurality of gate electrodes and the plurality of first gate wiring patterns along a third direction perpendicular to the first direction and the second direction; and
a plurality of source/drain wiring patterns provided in a second wiring layer, electrically connected to the plurality of source/drain regions, respectively, extending in parallel with the second direction, and overlapping the plurality of source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer,
wherein the first gate contact overlaps at least one of the plurality of source/drain wiring patterns along the third direction.
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