US 12,451,426 B2
Conductive traces in semiconductor devices and methods of forming same
Chao-Wen Shih, Zhubei (TW); Chen-Hua Yu, Hsinchu (TW); Han-Ping Pu, Taichung (TW); Hsin-Yu Pan, Taipei (TW); Hao-Yi Tsai, Hsinchu (TW); and Sen-Kuei Hsu, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 2, 2024, as Appl. No. 18/401,815.
Application 15/595,531 is a division of application No. 14/688,862, filed on Apr. 16, 2015, granted, now 9,653,406, issued on May 16, 2017.
Application 18/401,815 is a continuation of application No. 17/188,787, filed on Mar. 1, 2021, granted, now 11,894,299.
Application 17/188,787 is a continuation of application No. 15/595,531, filed on May 15, 2017, granted, now 10,937,734, issued on Mar. 2, 2021.
Prior Publication US 2024/0136280 A1, Apr. 25, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/525 (2006.01); H01L 23/532 (2006.01); H01L 23/552 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/525 (2013.01) [H01L 21/56 (2013.01); H01L 23/293 (2013.01); H01L 23/3192 (2013.01); H01L 23/5225 (2013.01); H01L 23/5329 (2013.01); H01L 23/552 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 21/76885 (2013.01); H01L 23/5286 (2013.01); H01L 24/13 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0348 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16104 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first polymer layer directly on an integrated circuit, wherein the integrated circuit comprises a contact pad over a first dielectric layer;
a first conductive line in the first polymer layer;
a second conductive line in the first polymer layer, wherein the first conductive line is thicker than the second conductive line, wherein an upper surface of the first conductive line is level with an upper surface of the second conductive line and an upper surface of the first polymer layer, wherein a portion of the first polymer layer extends completely under the first conductive line and the second conductive line in a cross-sectional view;
a protective layer over the first polymer layer; and
an under bump metallization layer extending through the protective layer, the under bump metallization layer being electrically coupled to the contact pad through a third conductive line and a via.