| CPC H01L 23/5226 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A vertical memory structure, comprising:
a stack of alternating layers of insulator material and layers of word line material;
a series of alternating conductive pillars and insulating pillars disposed through the stack, the series including at least a first conductive pillar, a first insulating pillar adjacent to the first conductive pillar and a second conductive pillar adjacent to the first insulating pillar, wherein an outside surface of the first insulating pillar is arcuate in a plane parallel to the layers of word line material;
data storage structures disposed on inside surfaces of the layers of word line material at cross-points of the first insulating pillar and the layers of word line material;
semiconductor channel material between the first insulating pillar and the data storage structures at cross-points of the first insulating pillar with the layers of word line material, the semiconductor channel material extending around the outside surface of the first insulating pillar and contacting the first conductive pillar and the second conductive pillar; and
conductor filled slots disposed in intervals along the series of alternating conductive pillars and insulating pillars, and extending through the stack to contact a conductive layer beneath the stack, wherein the conductor filled slots are elongated in a direction orthogonal to the series of alternating conductive pillars and insulating pillars.
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