US 12,451,421 B2
Semiconductor device with double etch stop layer and method of manufacturing the same
Sunyoung Noh, Suwon-si (KR); Euibok Lee, Suwon-si (KR); Wandon Kim, Seongnam-si (KR); Minjoo Lee, Suwon-si (KR); and Hyunbae Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 26, 2021, as Appl. No. 17/535,818.
Claims priority of application No. 10-2021-0006701 (KR), filed on Jan. 18, 2021.
Prior Publication US 2022/0230956 A1, Jul. 21, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/528 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate including an active region;
a first interlayer insulating layer disposed on the substrate;
a first wiring disposed in a plurality of trenches in the first interlayer insulating layer and electrically connected to the active region;
an insulating pattern disposed between adjacent trenches of the plurality of trenches on the first interlayer insulating layer and including a plurality of first openings, wherein the plurality of first openings expose the first wiring in the plurality of trenches, respectively;
a double etch stop layer including a lower etch stop pattern and an upper etch stop pattern,
wherein the lower etch stop pattern and the upper etch stop pattern are sequentially disposed on the insulating pattern and the first wiring such that the lower etch stop pattern directly contacts the first wiring, and
wherein the double etch stop layer includes a second opening that exposes a portion of the first wiring through one of the first openings and the lower etch stop pattern is spaced apart from the exposed portion of the first wiring;
a second interlayer insulating layer disposed on the upper etch stop pattern and including a via hole connected to the second opening, the via hole including a rounded top corner region;
a second wiring disposed in the via hole above the first wiring and within the second interlayer insulating layer; and
a via connecting the exposed portion of the first wiring and the second wiring to each other through the second opening and the via hole,
wherein the via has a first portion at least partially surrounded by the insulating pattern and a second portion located on the first portion and at least partially surrounded by the double etch stop layer and the second interlayer insulating layer, and
wherein a bottom of the first portion of the via includes a first stepped structure in which a width of the first portion is reduced from both side walls of the first portion that oppose each other.