US 12,451,416 B2
Electronic package and manufacturing method thereof
Jun-Hao Feng, Taichung (TW); and You-Chen Lin, Taichung (TW)
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD., Taichung (TW)
Filed by SILICONWARE PRECISION INDUSTRIES CO., LTD., Taichung (TW)
Filed on May 2, 2023, as Appl. No. 18/310,985.
Claims priority of application No. 111150977 (TW), filed on Dec. 30, 2022.
Prior Publication US 2024/0222250 A1, Jul. 4, 2024
Int. Cl. H01L 23/49 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H05K 1/18 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H05K 1/119 (2013.01); H05K 3/4602 (2013.01); H01L 25/0655 (2013.01); H01L 25/16 (2013.01); H05K 1/181 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10022 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10522 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a dielectric layer;
a conductive structure bonded to the dielectric layer;
a reinforced insulation portion bonded to the dielectric layer and abutting against the conductive structure, wherein the conductive structure is supported by the reinforced insulation portion; and
an electronic structure disposed on the dielectric layer and electrically connected to the conductive structure, wherein the electronic structure is supported by the dielectric layer and the reinforced insulation portion.