US 12,451,415 B2
Semiconductor device package, electronic assembly and method for manufacturing the same
Cheng-Lin Ho, Kaohsiung (TW); Chih-Cheng Lee, Kaohsiung (TW); Chun Chen Chen, Kaohsiung (TW); and Cheng Yuan Chen, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Sep. 19, 2023, as Appl. No. 18/370,320.
Application 18/370,320 is a continuation of application No. 17/140,926, filed on Jan. 4, 2021, granted, now 11,764,137.
Application 17/140,926 is a continuation of application No. 16/264,602, filed on Jan. 31, 2019, granted, now 10,886,208, issued on Jan. 5, 2021.
Claims priority of provisional application 62/745,222, filed on Oct. 12, 2018.
Prior Publication US 2024/0088001 A1, Mar. 14, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/49838 (2013.01); H05K 1/181 (2013.01); H05K 3/341 (2013.01); H05K 2201/10446 (2013.01); H05K 2201/10522 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An electronic assembly, comprising:
a structure including a substrate, a protection layer disposed on the substrate, and a conductive layer disposed on the substrate; and
a semiconductor device package electrically connected to the conductive layer by a connection element, wherein the semiconductor device package has a short side and has a long side substantially perpendicular to the substrate in a cross-sectional perspective,
wherein the protection layer exposes a portion of the conductive layer, and the connection element covers the portion of the conductive layer, and
wherein the semiconductor device package comprises:
a carrier and an electronic component disposed on a lateral surface of the carrier; and
a conductive structure connected to the carrier and the connection element, wherein an elevation of the conductive structure is lower than an elevation of the electronic component with respect to the substrate.