US 12,451,401 B2
Thermal dissipation in semiconductor devices
Wen-Sheh Huang, Hsinchu (TW); Yu-Hsiang Chen, Hsinchu (TW); and Chii-Ping Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 21, 2024, as Appl. No. 18/583,411.
Application 17/833,288 is a division of application No. 16/927,624, filed on Jul. 13, 2020, granted, now 11,355,410, issued on Jun. 7, 2022.
Application 18/583,411 is a continuation of application No. 17/833,288, filed on Jun. 6, 2022, granted, now 11,942,390.
Claims priority of provisional application 63/016,384, filed on Apr. 28, 2020.
Prior Publication US 2024/0194559 A1, Jun. 13, 2024
Int. Cl. H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 1/20 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/367 (2013.01) [H01L 23/3171 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H10D 1/20 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01); H01L 2224/0401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a layer of active devices;
a front-side interconnect structure on a front-side of the layer of active devices;
a backside interconnect structure on a backside of the layer of active devices, the backside interconnect structure comprising:
a first interconnect layer comprising a conductive line electrically connected to a source/drain region in the layer of active devices; and
a thermal dissipation path thermally connected to the layer of active devices, wherein the thermal dissipation path comprises a dummy via extending from a first metal line of the thermal dissipation path to a second metal line of the thermal dissipation path, wherein the front-side interconnect structure comprises a second thermal dissipation path thermally connected to the layer of active devices, wherein the second thermal dissipation path comprises a second dummy via extending from a third metal line of the second thermal dissipation path to a fourth metal line of the second thermal dissipation path.