US 12,451,399 B2
Integrated thermal solution to enable operation of embedded processors in sub-zero temperatures
Ganesh Kondapuram, Chandler, AZ (US); Chetan Rawal, Chandler, AZ (US); and Kevin Connolly, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 16, 2022, as Appl. No. 17/673,487.
Prior Publication US 2023/0260864 A1, Aug. 17, 2023
Int. Cl. H01L 23/34 (2006.01); G05D 23/19 (2006.01); G06F 9/4401 (2018.01); H01L 25/18 (2023.01); H05B 3/14 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/80 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/345 (2013.01) [G05D 23/1917 (2013.01); G06F 9/4403 (2013.01); H01L 25/18 (2013.01); H05B 3/148 (2013.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 84/811 (2025.01); H10D 89/105 (2025.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit die, comprising:
a substrate;
a device region, the device region comprising a plurality of semiconductor devices each comprising a source structure or a drain structure over the substrate, wherein the source structure or the drain structure comprises silicon or germanium and one or more of nickel, cobalt, tungsten, tantalum, titanium, platinum, palladium, or molybdenum; and
a resistive heating element over the substrate and within the device region or a second region, wherein the resistive heating element is coplanar with the source structure or the drain structure and comprises silicon or germanium and the one or more of nickel, cobalt, tungsten, tantalum, titanium, platinum, palladium, or molybdenum, and wherein the resistive heating element is to provide not less than 0.07 mW/mm2 to the integrated circuit die.