US 12,451,394 B2
Methods of manufacturing semiconductor chip including crack propagation guide
Hyo Sub Yeom, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 1, 2024, as Appl. No. 18/430,140.
Application 18/430,140 is a continuation of application No. 17/469,362, filed on Sep. 8, 2021, granted, now 11,923,247.
Claims priority of application No. 10-2021-0057547 (KR), filed on May 3, 2021.
Prior Publication US 2024/0170333 A1, May 23, 2024
Int. Cl. H01L 21/78 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 84/01 (2025.01)
CPC H01L 21/78 (2013.01) [H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 84/01 (2025.01)] 29 Claims
OG exemplary drawing
 
1. A semiconductor device comprising;
a first layer stack including alternately stacked first material layers and second material layers over a semiconductor substrate;
first crack propagation guides filling trenches, the trenches substantially penetrating the first layer stack;
a second layer stack including alternately stacked third material layers and fourth material layers on the first layer stack and the first crack propagation guides; and
second crack propagation guides filling openings, the openings substantially penetrating the second layer stack,
wherein the semiconductor substrate includes a chip region and the scribe lane region,
wherein cracks generated in a portion of the scribe lane region of the semiconductor substrate; and
wherein the cracks propagate to separate a semiconductor chip with the chip region from the semiconductor substrate.