US 12,451,393 B2
Etch stop layer for semiconductor devices
Szu-Ping Tung, Taipei (TW); Jen-Hung Wang, Hsinchu County (TW); and Shing-Chyang Pan, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Apr. 29, 2022, as Appl. No. 17/732,695.
Application 17/732,695 is a division of application No. 16/043,343, filed on Jul. 24, 2018, granted, now 11,322,396.
Application 16/043,343 is a division of application No. 15/197,294, filed on Jun. 29, 2016, granted, now 10,685,873, issued on Jun. 16, 2020.
Prior Publication US 2022/0254680 A1, Aug. 11, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76829 (2013.01) [H01L 21/76802 (2013.01); H01L 21/7682 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5222 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 21/76807 (2013.01); H01L 23/485 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a precursor having a substrate, a first dielectric layer over the substrate, and a first conductive feature in the first dielectric layer;
forming a silicon-containing dielectric layer over the first dielectric layer;
forming a metal-containing dielectric layer over the silicon-containing dielectric layer;
forming a second dielectric layer over the metal-containing dielectric layer; and
etching the second dielectric layer to form a first trench, the first trench exposing the metal-containing dielectric layer,
wherein the etching of the second dielectric layer etches the second dielectric layer faster than it etches the metal-containing dielectric layer.