US 12,451,385 B2
Wafer placement table
Masaki Ishikawa, Handa (JP); Tatsuya Kuno, Nagoya (JP); and Yusuke Ogiso, Nagakute (JP)
Assigned to NGK INSULATORS, LTD., Nagoya (JP)
Filed by NGK INSULATORS, LTD., Nagoya (JP)
Filed on Sep. 6, 2023, as Appl. No. 18/461,611.
Application 18/461,611 is a continuation of application No. PCT/JP2023/007066, filed on Feb. 27, 2023.
Prior Publication US 2024/0290646 A1, Aug. 29, 2024
Int. Cl. H01L 21/683 (2006.01); H01J 37/32 (2006.01)
CPC H01L 21/6833 (2013.01) [H01J 37/32715 (2013.01); H01J 2237/2007 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A wafer placement table comprising:
a ceramic plate having a wafer placement surface on an upper surface and a built-in electrode;
a plug placement hole extending through the ceramic plate from a lower surface to the upper surface;
a plug placed in the plug placement hole and allowing gas to pass therethrough; and
a plug joint joining an outer edge of an upper surface of the plug and an upper opening edge of the plug placement hole and covering the outer edge of the upper surface of the plug from above,
wherein, the plug placement hole is a tapered hole having a truncated conical space in which an upper opening area is larger than a lower opening area,
the plug is a truncated conical member in which an upper surface area is larger than a lower surface area,
the plug has a plug sloping surface at the outer edge of the upper surface,
the plug placement hole has a placement hole sloping surface at the upper opening edge, and
the plug joint is a thermal-sprayed portion filling a groove defined by the plug sloping surface and the placement hole sloping surface.