| CPC H01L 21/3212 (2013.01) [H01L 21/30625 (2013.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, comprising:
forming sacrificial gate structures over a substrate, wherein each of the sacrificial gate structures includes a sacrificial gate electrode and an upper portion of each of the sacrificial gate structures are exposed while a lower portion of each of the sacrificial gate structures is embedded in a first dielectric layer;
forming a second dielectric layer over the exposed sacrificial gate structures and over the first dielectric layer;
forming a third dielectric layer over the second dielectric layer;
performing a first planarization operation of the third and second dielectric layers such that the sacrificial gate electrodes are exposed and part of the second dielectric layer remains on the first dielectric layer;
removing the sacrificial gate electrode from each of the sacrificial gate structures, thereby forming gate spaces;
forming gate electrode structures in the gate spaces,
wherein the gate electrode structures are recessed in the gate spaces;
forming a fourth dielectric layer on each of the recessed gate electrode structures and over a remaining part of the second dielectric layer; and
performing a second planarization operation to remove part of the fourth dielectric layer,
wherein the remaining part of the second dielectric layer remains on the recessed first dielectric layer after the second planarization operation.
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