US 12,451,359 B2
Fluorine incorporation method for nanosheet
Hsin-Yi Lee, Hsinchu (TW); Mao-Lin Huang, Hsinchu (TW); Lung-Kun Chu, New Taipei (TW); Huang-Lin Chao, Hillsboro, OR (US); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 12, 2024, as Appl. No. 18/412,173.
Application 18/412,173 is a continuation of application No. 17/378,017, filed on Jul. 16, 2021, granted, now 11,915,937.
Claims priority of provisional application 63/181,595, filed on Apr. 29, 2021.
Prior Publication US 2024/0177996 A1, May 30, 2024
Int. Cl. H01L 21/28 (2025.01); H01L 21/3115 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01); H10D 30/67 (2025.01)
CPC H01L 21/28158 (2013.01) [H01L 21/3115 (2013.01); H10D 30/031 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 64/015 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first nanostructure, a sacrificial material, and a second nanostructure over a substrate;
removing the sacrificial material to form an opening between the first nanostructure and the second nanostructure;
depositing a first gate dielectric over the first nanostructure and a second gate dielectric over the second nanostructure;
depositing a first protective material over the first gate dielectric and a second protective material over the second gate dielectric;
flowing a fluorine-containing precursor and a reducing agent precursor over the first protective material and the second protective material;
removing the first protective material and the second protective material to expose the first gate dielectric and the second gate dielectric;
depositing a first conductive material over the first gate dielectric;
depositing a second conductive material over the first conductive material;
depositing a third conductive material over the second gate dielectric; and
depositing a fourth conductive material over the third conductive material.