US 12,451,352 B2
Method for fabricating semiconductor device
Doo Gyu Lee, Suwon-si (KR); Jeong Jin Lee, Suwon-si (KR); Min-Cheol Kwak, Suwon-si (KR); Seung Yoon Lee, Suwon-si (KR); and Chan Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 27, 2023, as Appl. No. 18/373,455.
Claims priority of application No. 10-2022-0183061 (KR), filed on Dec. 23, 2022.
Prior Publication US 2024/0213023 A1, Jun. 27, 2024
Int. Cl. H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 21/66 (2006.01)
CPC H01L 21/0273 (2013.01) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 22/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, the method comprising:
forming a lower pattern including a lower overlay key pattern having a first pitch, on a substrate;
forming an upper pattern including an upper overlay key pattern having a second pitch different from the first pitch, on the lower pattern;
measuring an overlay between the lower overlay key pattern and the upper overlay key pattern;
removing the upper overlay key pattern; and
performing an etching process using the upper pattern as an etching mask, after removing the upper overlay key pattern.
 
9. A method for fabricating a semiconductor device, the method comprising:
providing a substrate including a cell region and an overlay key region;
forming a lower pattern including a lower cell pattern on the cell region and a lower overlay key pattern on the overlay key region, the lower overlay key pattern having a first pitch;
forming an upper pattern including an upper cell pattern on the lower cell pattern and an upper overlay key pattern on the lower overlay key pattern, the upper overlay key pattern having a second pitch different from the first pitch;
measuring an overlay between the lower overlay key pattern and the upper overlay key pattern, using a Moire pattern formed by the lower overlay key pattern and the upper overlay key pattern;
removing the upper overlay key pattern; and
after removing the upper overlay key pattern, performing an etching process using the upper cell pattern as an etch mask, wherein an etch endpoint of the etching process is lower than an upper face of the lower cell pattern.
 
16. A method for fabricating a semiconductor device, the method comprising:
providing a substrate including a cell region and an overlay key region;
forming a lower pattern including a lower cell pattern on the cell region and a lower overlay key pattern on the overlay key region, the lower overlay key pattern having a first pitch;
forming an upper pattern including an upper cell pattern on the lower cell pattern and an upper overlay key pattern on the lower overlay key pattern, the upper overlay key pattern having a second pitch different from the first pitch;
removing the upper overlay key pattern; and
after removing the upper overlay key pattern, performing an etching process using the upper cell pattern as an etching mask to remove at least a part of the lower cell pattern.