US 12,451,347 B2
Semiconductor processing method
Wangyu Lim, Hwaseong-si (KR); Heesung Kang, Anyang-si (KR); Jaeok Ko, Seoul (KR); Jaebin Ahn, Suwon-si (KR); Sunja Kim, Hwaseong-si (KR); Youngjae Kim, Cheonan-si (KR); and Donghyun Ko, Hwaseong-si (KR)
Assigned to ASM IP Holding B.V., Almere (NL)
Filed by ASM IP Holding B.V., Almere (NL)
Filed on Mar. 22, 2022, as Appl. No. 17/701,433.
Claims priority of provisional application 63/166,152, filed on Mar. 25, 2021.
Prior Publication US 2022/0310387 A1, Sep. 29, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/764 (2006.01)
CPC H01L 21/02312 (2013.01) [H01L 21/764 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A substrate processing method comprising:
forming a protective layer on a pattern structure including an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface;
supplying a fluorine-containing gas under a first plasma condition comprising a first frequency and first process pressure to form fluorine-terminated sites on the protective layer;
purging the fluorine-containing gas;
supplying a hydrogen-containing gas under a second plasma condition comprising a second frequency higher than the first frequency and second process pressure higher than the first process pressure to form hydrogen-terminated sites on the protective layer;
purging the hydrogen-containing gas;
supplying a silicon-containing source gas to form Si—H-terminated sites, wherein the forming of the Si—H-terminated sites is promoted on the hydrogen-terminated sites and inhibited on the fluorine-terminated sites;
purging the silicon-containing source gas;
forming an interlayer insulating layer on the protective layer by supplying a reactive gas having reactivity with the Si—H-terminated sites; and
purging the reactive gas.