US 12,451,290 B2
Capacitor
Yosuke Hagihara, Osaka (JP); and Kazushi Yoshida, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Appl. No. 18/555,475
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
PCT Filed Mar. 22, 2022, PCT No. PCT/JP2022/013168
§ 371(c)(1), (2) Date Oct. 13, 2023,
PCT Pub. No. WO2022/224669, PCT Pub. Date Oct. 27, 2022.
Claims priority of application No. 2021-072069 (JP), filed on Apr. 21, 2021.
Prior Publication US 2024/0203654 A1, Jun. 20, 2024
Int. Cl. H01G 4/228 (2006.01); H01G 4/33 (2006.01)
CPC H01G 4/228 (2013.01) [H01G 4/33 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A capacitor comprising:
a silicon substrate having:
a principal surface including an opening region and a non-opening region other than the opening region, and
a porous part having an opening in the opening region;
at least one first terminal electrically connected to the silicon substrate;
a dielectric layer on an inner surface of the porous part;
a conductive portion filled, on the dielectric layer, in the porous part; and
at least one second terminal electrically connected to the conductive portion,
at least one of the at least one first terminal or the at least one second terminal overlapping at least part of the porous part in a normal direction of the principal surface,
the at least one first terminal including a plurality of first terminals,
the at least one second terminal including a plurality of second terminals,
the capacitor further comprising a wire electrically connecting the plurality of first terminals to each other, and
the wire having electrical resistivity lower than electrical resistivity of the silicon substrate.