US 12,451,284 B2
Multilayer board, electronic device, and multilayer board inspection method
Kiminori Kouno, Nagaokakyo (JP); and Koji Kamada, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on May 23, 2022, as Appl. No. 17/750,430.
Application 17/750,430 is a continuation of application No. PCT/JP2021/002270, filed on Jan. 22, 2021.
Claims priority of application No. 2020-009818 (JP), filed on Jan. 24, 2020.
Prior Publication US 2022/0285082 A1, Sep. 8, 2022
Int. Cl. H01F 5/00 (2006.01); H01F 27/28 (2006.01); H01F 27/29 (2006.01); H05K 1/02 (2006.01); H05K 1/16 (2006.01); H05K 3/46 (2006.01)
CPC H01F 27/2804 (2013.01) [H01F 27/292 (2013.01); H05K 1/0268 (2013.01); H05K 1/165 (2013.01); H05K 3/4632 (2013.01); H01F 2027/2809 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A multilayer board comprising:
a first insulator layer including a first coil pattern thereon;
a second insulator layer including a second coil pattern thereon;
a third insulator layer including a third coil pattern thereon;
a first terminal on the first insulator layer and connected to one end of the first coil pattern;
a first floating pattern on the first insulator layer and not connected to the first coil pattern; and
a second terminal electrically connected to one end of the third coil pattern; wherein
the first insulator layer, the second insulator layer, and the third insulator layer are sequentially laminated;
the first coil pattern, the second coil pattern, and the third coil pattern are respectively electrically connected in sequence; and
the first floating pattern overlaps the second coil pattern when viewed from a laminating direction.