US 12,451,212 B2
Device, system and method for memory repair with multi-cell switching
Aravinda Radhakrishnan, Sunnyvale, CA (US); Marcus Wing-Kin Cheung, Cupertino, CA (US); Dinesh Somasekhar, Portland, OR (US); Naga Mallika Bhandaru, Fremont, CA (US); Michael Nelms, Fort Collins, CO (US); Rodrigo Gonzalez Gutierrez, Hillsboro, OR (US); and Kaitlyn Chen, Hillsboro, OR (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Jun. 25, 2020, as Appl. No. 16/912,498.
Prior Publication US 2021/0407618 A1, Dec. 30, 2021
Int. Cl. G11C 29/00 (2006.01); G11C 5/14 (2006.01)
CPC G11C 29/702 (2013.01) [G11C 5/147 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of memory cells, wherein a column of the array comprises first memory cells and second memory cells;
control circuitry to receive a signal comprising an identifier of a defective memory cell of the first memory cells, wherein the control circuitry comprises multiple control circuits, each of the multiple control circuits comprising a respective first AND gate and a respective second AND gate, coupled to each other in a daisy chain configuration, and wherein a second AND gate of one of the multiple control circuits is coupled to a second AND gate of a subsequent one of the multiple control circuits, the multiple control circuits each to generate a different respective one of the control signals;
switch circuitry coupled to communicate data signals between signal lines and the column, wherein, responsive to the control circuitry, the switch circuitry is to transition to a state wherein:
for each signal line of first multiple ones of the signal lines, the signal line is switchedly decoupled from the first memory cells, based on the identifier, and the signal line is coupled to a respective one of the second memory cells; and
for each signal line of second multiple ones of the signal lines, the signal line is switchedly coupled to a respective one of the first memory cells based on the identifier, wherein the switch circuitry comprises 1:2 or 2:1 multiplexer circuits each coupled to a different respective two memory cells of the column, and wherein, based on the identifier, the control circuitry is to generate control signals each to operate a different respective one of the multiplexer circuits.