| CPC G11C 29/52 (2013.01) [G11C 29/022 (2013.01); G11C 29/886 (2013.01)] | 18 Claims |

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1. A data storage device comprising:
a memory; and
one or more processors, individually or in combination, configured to:
receive a command from a host to exit a low-power mode; and
in response to receiving the command from the host to exit the low-power mode:
use firmware randomization logic to perform a randomization process to randomly select a single wordline from a set of wordlines in the memory designated for an active read scan;
perform a bit error rate (BER) check on the randomly-selected single wordline and its two directly adjacent neighbor wordlines;
determine whether there is a BER failure on the randomly-selected single wordline or its two directly adjacent neighbor wordlines; and
in response to determining that there is a BER failure on the randomly-selected single wordline or its two directly adjacent neighbor wordlines, perform a BER estimation scan (BES) of the memory.
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