US 12,451,208 B2
Charge loss tracking through targeted bit count
Steven Michael Kientz, Westminster, CO (US); Pitamber Shukla, San Jose, CA (US); and Tarun Singh Yadav, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 26, 2024, as Appl. No. 18/647,731.
Claims priority of provisional application 63/462,709, filed on Apr. 28, 2023.
Prior Publication US 2024/0363188 A1, Oct. 31, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/50004 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory component comprising a plurality of memory cells; and
a processing device programmed to perform operations comprising:
determining, for the memory component, a first count fail byte (CFByte) value at a first threshold voltage;
determining a second threshold voltage based on the first threshold voltage and a predetermined offset;
determining, for the memory component, a second CFByte value at the second threshold voltage;
determining a slope based on the predetermined offset, the first CFByte value, and the second CFByte value;
determining a third voltage based on the slope and a target CFByte value; and
using the third voltage as a threshold voltage for the memory component.