US 12,451,207 B2
Semiconductor devices for detecting defects in error correction circuits, and methods of performing test mode operations
Hyun Seung Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 18, 2023, as Appl. No. 18/489,567.
Claims priority of application No. 10-2023-0072363 (KR), filed on Jun. 5, 2023.
Prior Publication US 2024/0404616 A1, Dec. 5, 2024
Int. Cl. G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/46 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a read circuit configured to latch read parity including error information on read data output from a memory circuit to generate latch parity when a test read control signal is enabled;
a parity selection circuit configured to output the latch parity as parity when a test selection signal is enabled; and
a write circuit configured to receive write data generated from data and the parity, and to correct error of the write data, based on write parity including error information on the write data and the parity to generate correction data when a test write control signal is enabled.