US 12,451,206 B2
Extending functionality of memory controllers using a loopback mode for testing in a processor-based device
Massimo Sutera, Sunnyvale, CA (US); Rakesh Kumar, Cupertino, CA (US); Kha Minh Huynh, Ho Chi Minh (VN); Sandeep Brahmadathan, Dublin, CA (US); Anil Kumar Handenahalli Rajanna, San Jose, CA (US); and Nagi Aboulenein, King City, OR (US)
Assigned to Ampere Computing LLC, Santa Clara, CA (US)
Filed by Ampere Computing LLC, Santa Clara, CA (US)
Filed on Oct. 18, 2023, as Appl. No. 18/381,568.
Prior Publication US 2025/0131970 A1, Apr. 24, 2025
Int. Cl. G11C 7/00 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/42 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor-based device, comprising:
a memory controller;
a physical (PHY) interface circuit communicatively coupled to the memory controller, wherein the PHY interface circuit is configured to operate in a loopback mode; and
a memory access intercept circuit configured to operate in the loopback mode by being configured to:
receive, from a requestor, a memory write request that is directed to and received by the memory controller;
transmit proxy write data to the memory controller;
intercept write data from the requestor directed to the memory controller for the memory write request;
store the write data in a write data buffer;
intercept the proxy write data from the memory controller directed to the PHY interface circuit;
retrieve the write data from the write data buffer;
transmit the write data to the PHY interface circuit;
receive, from the PHY interface circuit, loopback data directed to the memory controller in response to a read signal from the memory access intercept circuit; and
store the loopback data in a read data buffer.