US 12,451,205 B2
Fuse memory circuit
Masanobu Tsuji, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Dec. 26, 2023, as Appl. No. 18/396,118.
Application 18/396,118 is a continuation of application No. PCT/JP2022/024376, filed on Jun. 17, 2022.
Claims priority of application No. 2021-107096 (JP), filed on Jun. 28, 2021.
Prior Publication US 2024/0136004 A1, Apr. 25, 2024
Prior Publication US 2024/0233845 A9, Jul. 11, 2024
Int. Cl. G11C 17/00 (2006.01); G11C 17/16 (2006.01)
CPC G11C 17/165 (2013.01) 10 Claims
OG exemplary drawing
 
1. A fuse memory circuit comprising:
a first line being one of a power supply line and a ground line;
a second line being the other of the power supply line and the ground line;
a first fuse unit; and
a second fuse unit,
wherein the first fuse unit and the second fuse unit each comprise:
a test terminal;
a program terminal;
an output terminal;
a fuse element having a first end coupled to the first line;
a rectification element coupled in parallel with the fuse element;
a first transistor having a drain coupled to a second end of the fuse element, a source coupled to the second line, and a gate coupled to the program terminal;
a second transistor having a source coupled to the second end of the fuse element, a drain coupled to the output terminal, and a gate coupled to the test terminal; and
a third transistor having a drain coupled to the output terminal, and a source coupled to the second line,
wherein a gate of the third transistor of the first fuse unit is coupled to the output terminal of the second fuse unit,
and wherein a gate of the third transistor of the second fuse unit is coupled to the output terminal of the first fuse unit.