US 12,451,203 B2
Memory device and method of operating the memory device
Jae Woong Kim, Icheon-si (KR); and Kyu Nam Lim, Icheon-si (KR)
Assigned to SK hynix Inc., Incheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/521,063.
Claims priority of application No. 10-2023-0069198 (KR), filed on May 30, 2023.
Prior Publication US 2024/0404609 A1, Dec. 5, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block;
a peripheral circuit configured to increase a threshold voltage of memory cells selected among memory cells included in the memory block according to logic data, detect low-level cells having a threshold voltage higher than a reference voltage among memory cells having a threshold voltage lower than a verify voltage at a first time within a verify time set according the number of bits included in the logic data, and detect high-level cells having a threshold voltage higher than the verify voltage at a second time after the first time; and
a control circuit configured to control the peripheral circuit in response to a command.