US 12,451,202 B2
Memory device with sub-processor for parallel control of program voltage and pass/fail check and method of operating the same
Byoung In Joo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 19, 2023, as Appl. No. 18/320,200.
Claims priority of application No. 10-2022-0167018 (KR), filed on Dec. 2, 2022.
Prior Publication US 2024/0185932 A1, Jun. 6, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/12 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/12 (2013.01); G11C 16/24 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
memory cells coupled between a word line and bit lines;
a main processor configured to control program-related voltages that are applied to the word line and the bit lines, and to generate a control signal after controlling a voltage to be applied to the bit lines and before controlling a program voltage to be applied to the word line;
a page buffer configured to store data sensed based on threshold voltages of the memory cells;
a sensing circuit configured to perform a pass/fail check operation of comparing a sensing current corresponding to the sensed data with a reference current; and
a sub-processor configured to control the page buffer and the sensing circuit to perform the pass/fail check operation in response to the control signal, in parallel with control of the program-related voltages while the main processor controls the program-related voltages.