US 12,451,201 B2
Hybrid precharge select scheme to save program ICC
Wei Zhao, Fremont, CA (US); and Henry Chin, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies, Inc., Milpitas, CA (US)
Filed on Jun. 21, 2022, as Appl. No. 17/845,318.
Prior Publication US 2023/0410923 A1, Dec. 21, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a non-volatile memory including control circuitry and an array of memory cells that are arranged in a plurality of word lines and are coupled to a plurality of bitlines;
a controller coupled to the non-volatile memory, the controller being configured to:
during a first program loop for programming a first set of memory cells of a selected word line of the plurality of word lines to a first set of states of a plurality of states, select a first bitline precharging mode, the first bitline precharging mode including consecutively precharging the bitlines of the first set of bitlines prior to verifying each state of the first set of states, and
during a second program loop for programming a second set of memory cells in the selected word line to a second set of states of the plurality of states, select a second bitline precharging mode, the second bitline precharging mode including simultaneously precharging only the bitlines of the second set of bit lines prior to verifying the second set of states.