US 12,451,200 B2
Memory device related to verifying memory cells in an erase state and method of operating the memory device
Hyung Jin Choi, Icheon-si (KR); and Chan Sik Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 28, 2023, as Appl. No. 18/191,807.
Claims priority of application No. 10-2022-0147871 (KR), filed on Nov. 8, 2022.
Prior Publication US 2024/0153568 A1, May 9, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/102 (2013.01); G11C 16/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
memory cells coupled to a word line;
a peripheral circuit configured to perform a program operation of increasing threshold voltages of the memory cells to threshold voltages corresponding to a target program state among a plurality of program states; and
a program operation controller configured to, after the program operation is performed, determine whether to perform an erase state verify operation of identifying threshold voltages of erase cells having an erase state as the target program state among the memory cells depending on a highest voltage among program voltages applied to the word line in the program operation,
wherein the program operation controller is configured to determine whether to perform the erase state verify operation based on a result of comparing the magnitude of the highest voltage among the program voltages with the magnitude of the reference voltage.