US 12,451,199 B2
Semiconductor memory device performing program operation and method of operating the same
Kwang Min Lim, Icheon-si (KR); and Hee Youl Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 31, 2024, as Appl. No. 18/679,914.
Application 18/679,914 is a continuation of application No. 17/365,718, filed on Jul. 1, 2021, granted, now 12,073,893.
Claims priority of application No. 10-2021-0001137 (KR), filed on Jan. 5, 2021.
Prior Publication US 2024/0321365 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory blocks, wherein the plurality of memory blocks are connected to a common source line commonly, each of the plurality of memory blocks is connected to a first source select line connected to first source select transistors and a second source select line connected to second source select transistors, the first source select line is adjacent to the second source select line in each of the plurality of memory blocks, and the second source select line is located closer to the common source line than the first source select line;
a peripheral circuit configured to perform a program operation on a selected memory block among the plurality of memory blocks; and
control logic configured to control the program operation of the peripheral circuit,
wherein the program operation comprises a plurality of program loops, each program loop includes a channel precharge operation and a program pulse application operation following the channel precharge operation, and the channel precharge operation includes a first precharge operation and a second precharge operation following the first precharge operation,
wherein, during the first precharge operation, the control logic is configured to control the peripheral circuit to apply a predetermined voltage to the common source line, and
wherein, during the second precharge operation, the control logic is configured to control the peripheral circuit to allow the common source line to float and to increase a voltage of the second source select line connected to an unselected memory block among the plurality of memory blocks while maintaining a voltage of the first source select line connected to the unselected memory block turning off the first source select transistors.