US 12,451,198 B2
In-memory read threshold adaptation
Pengfei Huang, San Jose, CA (US); and Fan Zhang, Fremont, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 3, 2024, as Appl. No. 18/403,019.
Prior Publication US 2025/0218523 A1, Jul. 3, 2025
Int. Cl. G11C 16/34 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01)
CPC G11C 16/3404 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/42 (2013.01); G11C 2029/1802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by a memory device of a storage device that includes a memory controller coupled to the memory device, the method comprising:
performing, for each entry of a set of entries of an in-memory history read retry (HRR) table, a test read of the memory device using a set of read thresholds corresponding to that entry;
identifying an entry in the set of entries having a lowest failed bit count (FBC) obtained from the test read of each entry;
updating the in-memory HRR table to have the identified entry with the lowest FBC be at a beginning of the in-memory HRR table; and
notifying the memory controller to update an in-controller HRR table stored in the memory controller based on the update to the in-memory HRR table, wherein each entry in the in-controller HRR table stores an index that references a corresponding set of read thresholds in a read thresholds table stored in the memory device.