US 12,451,197 B2
Adaptive integrity scan rates in a memory sub-system based on block health metrics
Vamsi Pavan Rayaprolu, Santa Clara, CA (US); Christopher M. Smitchger, Boise, ID (US); James Fitzpatrick, Laguna Niguel, CA (US); Patrick R. Khayat, San Diego, CA (US); and Sampath K. Ratnam, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,859.
Prior Publication US 2024/0062835 A1, Feb. 22, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/34 (2013.01) [G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method comprising:
detecting an occurrence of a data integrity check trigger event;
responsive to the occurrence of the data integrity check trigger event, identifying a memory die of a plurality of memory dies;
associating each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms; and
determining one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.