| CPC G11C 16/26 (2013.01) [G11C 7/06 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a first chip including a first memory cell array including a first memory cell;
a second chip including a second memory cell array including a second memory cell; and
a third chip including a row decoder and a sense amplifier, wherein
the first memory cell and the second memory cell are commonly connected to the row decoder via a first word line,
the first memory cell is connected to the sense amplifier via a first bit line,
the second memory cell is connected to the sense amplifier via a second bit line, and
the sense amplifier includes a first node selectively connectable to the first bit line and the second bit line and is configured to sense a voltage at the first node to read data stored in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data stored in the second memory cell when the first node is connected to the second bit line.
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