US 12,451,193 B2
Memory system, memory and memory control method
Yi Cao, Hubei (CN); Ke Liang, Hubei (CN); and Liang Qiao, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Jun. 6, 2023, as Appl. No. 18/330,120.
Claims priority of provisional application 63/477,882, filed on Dec. 30, 2022.
Claims priority of application No. 202310587250.9 (CN), filed on May 23, 2023.
Prior Publication US 2024/0221842 A1, Jul. 4, 2024
Int. Cl. G11C 16/20 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array; and
a peripheral circuit, comprising:
a page buffer coupled to the memory array and configured to detect fail-bits in the memory array;
a verify fail-bit count (VFC) circuit coupled to the page buffer, wherein the VFC circuit includes a comparator unit configured to determine a mismatch and a trimming unit configured to generate an offset signal to compensate the mismatch in the VFC circuit such that the VFC circuit outputs a quantity of the fail-bits in the memory array, wherein the trimming unit is further configured to:
decrease the offset signal, if the mismatch is positive; and
increase the offset signal, if the mismatch is negative; and
a control circuit coupled to the VFC circuit and configured to control an adjustment of the offset signal.