| CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 41/41 (2023.02); H10B 43/40 (2023.02); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
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1. A non-volatile memory device comprising:
a memory cell array comprising a plurality of memory cells in which each memory cell is connected to a respective bit line from a plurality of bit lines that extend in a first direction, and comprise first to twelfth bit lines arranged in a second direction different from the first direction; and
a page buffer circuit disposed below the memory cell array in a vertical direction different from the first direction and the second direction and having a multi-stage structure in the first direction,
wherein a stage of the multi-stage structure comprises:
a high voltage region comprising a first high voltage transistor connected to one of first to sixth bit lines from the plurality of bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines from the plurality of bit lines,
a first low voltage region adjacent to the high voltage region in the first direction, and the first low voltage region comprising a first transistor connected to the first high voltage transistor, and
a second low voltage region adjacent to the high voltage region in the first direction and adjacent to the first low voltage region in the second direction, and the second low voltage region comprising a second transistor connected to the second high voltage transistor,
wherein each of the first low voltage region and the second low voltage region has a first width corresponding to a pitch of six bit lines in the second direction, and
wherein the high voltage region has a second width corresponding to a pitch of twelve bit lines in the second direction.
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