US 12,451,189 B2
Partial block handling protocol in a non-volatile memory device
Zhongguang Xu, San Jose, CA (US); Tingjun Xie, Milpitas, CA (US); and Murong Lang, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 21, 2024, as Appl. No. 18/670,073.
Application 18/670,073 is a continuation of application No. 17/825,439, filed on May 26, 2022, granted, now 12,027,211.
Prior Publication US 2024/0312526 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
logically closing a block of the memory device to prevent additional program operations from being performed on the block;
causing one or more wordlines of the block to be programmed with padding data, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed; and
causing a remaining set of wordlines of the block to be concurrently programmed to a single program state.