	US 12,451,184 B2
	Semiconductor device
Venkateswara Reddy Konudula, Hsinchu (TW); Teja Masina, Hsinchu (TW); Nikhil Puri, Hsinchu (TW); Yen-Huei Chen, Hsinchu County (TW); and Hung-Jen Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 24, 2023, as Appl. No. 18/189,971.
Claims priority of provisional application 63/380,950, filed on Oct. 26, 2022.
Prior Publication US 2024/0144997 A1, May 2, 2024
Int. Cl. G11C 11/419 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01)

CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H10B 10/12 (2023.02)]

20 Claims

1. A semiconductor device, comprising:

a first memory array;

a first bit line crossing over and coupled to the first memory array, and extending along a first direction;

a second memory array;

a second bit line crossing over the second memory array, and coupled to the first bit line;

a first conductive line crossing over the second memory array and a part of the first memory array, and configured to operate as a part of a first capacitor; and

a first control circuit configured to turn on a first switch coupled between the first conductive line and the second bit line according to a first control signal which indicates whether the first memory array is written or not, to couple the first conductive line to the second bit line when the first memory array is written.