US 12,451,183 B2
Burst access memory and method of operating a burst access memory
Babak Mohammadi, Lund (SE)
Assigned to XENERGIC AB, Lund (SE)
Appl. No. 18/558,695
Filed by XENERGIC AB, Lund (SE)
PCT Filed May 5, 2022, PCT No. PCT/EP2022/062099
§ 371(c)(1), (2) Date Nov. 2, 2023,
PCT Pub. No. WO2022/233993, PCT Pub. Date Nov. 10, 2022.
Claims priority of application No. 21172323 (EP), filed on May 5, 2021.
Prior Publication US 2024/0242761 A1, Jul. 18, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/418 (2013.01) [G11C 11/412 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A burst access memory comprising:
a memory array comprising a plurality of memory macros, each memory macro comprising an array of memory cells without read/write logic arranged in rows and columns, wherein the memory cells in each column are connected by at least one local bit line, said array of memory cells and the local bit lines defining the memory macro;
a controller configured to schedule a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros, wherein the plurality of macro accesses are scheduled to start with a predefined delay in relation to each other,
wherein the burst access memory comprises a plurality of global bit lines and bit line switches, wherein each global bit line is connectable to several corresponding local bit lines of the memory macros; and
wherein each macro access is divided into a plurality of ordered sub-operations, and wherein consecutive macro accesses are directed to different memory macros and different columns, wherein data for consecutive macro accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses.