| CPC G11C 11/4093 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4087 (2013.01)] | 20 Claims |
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1. A nonvolatile memory device comprising:
a first semiconductor layer comprising:
a plurality of word-lines extending in a first direction;
a plurality of bit-lines extending in a second direction that crosses the first direction; and
a memory cell array comprising one or more memory blocks spaced apart from each other in the second direction, one or more dummy blocks between the one or more memory blocks and a through-hole via region, the memory cell array being connected to the plurality of word-lines and the plurality of bit-lines; and
a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer comprising:
a substrate;
an address decoder configured to control the memory cell array;
a page buffer circuit connected to the plurality of bit-lines through one or more bit-line through-hole vias formed in the through-hole via region; and
a control circuit configured to control the address decoder and the page buffer circuit,
wherein each of the one or more dummy blocks inte-includes an adjacent sub-block directly contacting the through-hole via region and a non-adjacent sub-block which are divided based on a relative distance from the through-hole via region in the second direction,
wherein the control circuit is further configured to use the non-adjacent sub-block of each of the one or more dummy blocks as a sub-block to store data, and
wherein the one or more memory blocks are separated from the one or more dummy blocks by word-line cut regions extending in the first direction.
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