US 12,451,181 B2
Bitline sense amplifier with equalizing transistor and a memory device
Soo Bong Chang, Incheon (KR); Young-Il Lim, Suwon-si (KR); Bok-Yeon Won, Namyangju-si (KR); Seok Jae Lee, Gwangmyeong-si (KR); Dong Geon Kim, Suwon-si (KR); Myeong Sik Ryu, Anyang-si (KR); In Seok Baek, Suwon-si (KR); Kyoung Min Kim, Namyangju-si (KR); and Sang Wook Park, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 18, 2024, as Appl. No. 18/607,646.
Application 18/607,646 is a division of application No. 17/585,865, filed on Jan. 27, 2022, granted, now 11,961,551.
Prior Publication US 2024/0221824 A1, Jul. 4, 2024
Int. Cl. G11C 11/4091 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4094 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A bitline sense amplifier, comprising:
an equalizing enable transistor which has a first end connected to a first supply line to precharge a first bitline and a second bitline with a precharge voltage in response to an equalizing control signal;
a first supply transistor which provides the first supply voltage to the first supply line in response to a first control signal; and
an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between the first bitline and the second bitline in response to the first control signal and a second control signal,
wherein the equalizing enable transistor and the first supply transistor share a single active region.