US 12,451,180 B2
Offset cancellation method and method of preventing noise generated during sensing and amplification
Weibing Shang, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Aug. 3, 2023, as Appl. No. 18/230,112.
Application 18/230,112 is a continuation of application No. PCT/CN2022/124155, filed on Oct. 9, 2022.
Claims priority of application No. 202211042478.1 (CN), filed on Aug. 29, 2022.
Prior Publication US 2024/0071474 A1, Feb. 29, 2024
Int. Cl. G11C 11/401 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for controlling a sense amplifier, wherein the sense amplifier comprises a first N-type transistor, a second N-type transistor, a first P-type transistor, and a second P-type transistor; a drain of the first N-type transistor, a drain of the first P-type transistor, and a gate of the second P-type transistor are connected to a first node; a drain of the second N-type transistor, a drain of the second P-type transistor, and a gate of the first P-type transistor are connected to a second node; a gate of the first N-type transistor is connected to a bit line and a gate of the second N-type transistor is connected to a complementary bit line; a source of the first P-type transistor and a source of the second P-type transistor are configured to connect to a power supply voltage, and a source of the first N-type transistor and a source of the second N-type transistor are configured to connect to ground; and the method for controlling the sense amplifier chronologically comprises an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing and amplification phase that occur in sequence, wherein:
in the charge sharing phase, during which an activation signal is input to a word line corresponding to a storage unit connected to the sense amplifier, controlling the first node to connect to the complementary bit line for a first predetermined duration and controlling the second node to connect to the bit line for the first predetermined duration, and then disconnecting the connection between the bit line and the second node and the connection between the first node and the complementary bit line; and
in the sensing and amplification phase, in response to detecting that a voltage on the first node or a voltage on the second node reaches a predetermined voltage, controlling the first node to connect to the complementary bit line and the second node to connect to the bit line, to transmit an amplified voltage to the bit line and the complementary bit line.