US 12,451,179 B2
Refresh window aware truncation of restore voltages for random access memory
Darshan Kumar Nandanwar, Bangalore (IN); Arvind Garg, Bangalore (IN); and Sanku Mukherjee, Bangalore (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 2, 2024, as Appl. No. 18/402,115.
Prior Publication US 2025/0218486 A1, Jul. 3, 2025
Int. Cl. G11C 11/406 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40603 (2013.01); G11C 11/4076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by memory control circuitry for control of memory charge restoration of a memory, comprising:
determining a time position within a refresh window of a read operation of at least one memory cell of the memory;
charging the at least one memory cell to a first voltage that is based on the time position of the read operation within the refresh window; and
re-charging the at least one memory cell to a full voltage upon termination of the refresh window,
wherein the first voltage is less than the full voltage in a first portion of the refresh window.