US 12,451,178 B2
Synapse device and method of operating the same
Yoonyoung Chung, Pohang-si (KR); Suwon Seong, Yongin-si (KR); and Seongmin Park, Pohang-si (KR)
Assigned to POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION, Pohang-si (KR)
Filed by POSTECH Research and Business Development Foundation, Pohang-si (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/522,109.
Claims priority of application No. 10-2022-0177321 (KR), filed on Dec. 16, 2022.
Prior Publication US 2024/0203473 A1, Jun. 20, 2024
Int. Cl. G11C 11/405 (2006.01); G06N 3/065 (2023.01); G11C 11/4096 (2006.01); G11C 11/54 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/405 (2013.01) [G06N 3/065 (2023.01); G11C 11/4096 (2013.01); G11C 11/54 (2013.01); H10B 12/00 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A synapse device, comprising:
an oxide semiconductor transistor divided into a write transistor and a read transistor,
wherein the write transistor is an oxide semiconductor transistor including a dual gate comprising:
a bottom gate located below a thin oxide semiconductor layer; and
a top gate located above the thin oxide semiconductor layer.