US 12,451,177 B2
Time tracking circuit for FRAM
David J. Toops, Lucas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 24, 2022, as Appl. No. 17/751,841.
Application 17/751,841 is a continuation of application No. 17/108,041, filed on Dec. 1, 2020, abandoned.
Application 17/108,041 is a continuation of application No. 16/404,118, filed on May 6, 2019, granted, now 10,854,265, issued on Dec. 1, 2020.
Application 16/404,118 is a continuation of application No. 15/057,475, filed on Mar. 1, 2016, granted, now 10,283,181, issued on May 7, 2019.
Prior Publication US 2022/0284940 A1, Sep. 8, 2022
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2293 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
performing a read operation on a capacitive memory array that includes a set of bit line input/outputs, a set of word line inputs, and a set of plate inputs by:
providing a first signal to a row driver circuit;
based on the first signal, applying, using the row driver circuit, a first voltage to at least a subset of the set of word line inputs;
providing a second signal to a plate driver circuit a first delay after the providing of the first signal;
based on the second signal, applying, using the plate driver circuit, a second voltage to at least a subset of the set of plate inputs, wherein the first delay associated with the second signal is less than minimum amount of read delay associated with the set of plate inputs of the capacitive memory array and the applying of the second voltage is performed after the minimum amount of read delay associated with the set of plate inputs of the capacitive memory array; and
receiving a value via the set of bit line input/outputs.