| CPC G11C 11/1677 (2013.01) [G11C 5/063 (2013.01); G11C 7/04 (2013.01); G11C 11/1673 (2013.01)] | 18 Claims | 

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               1. A nonvolatile memory device comprising: 
            a memory cell array including a plurality of memory cells; 
                a plurality of bit lines and a plurality of word lines connected with the plurality of memory cells; 
                a common source line connected with the plurality of memory cells; 
                a control logic circuit including a common source line noise control logic circuit, and configured to generate a plurality of voltages including a first voltage and a second voltage; 
                a voltage selector configured to receive the plurality of voltages and to select at least one of the plurality of voltages; and 
                a common source line driver configured to receive the at least one selected voltage and to control a voltage of the common source line, 
                wherein the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the plurality of voltages, 
                the common source line driver includes a first transistor, and 
                the voltage selector is configured to select the first voltage as a gate voltage of the first transistor. 
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