| CPC G11C 11/161 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H10B 61/22 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02); H10N 52/01 (2023.02); H10N 52/101 (2023.02); H10N 52/80 (2023.02)] | 20 Claims |

|
1. A method, comprising:
forming bottom electrode vias (BEVAs) in a dielectric layer;
depositing a bottom electrode layer on the BEVAs;
depositing a first ferromagnetic free layer on the bottom electrode layer;
depositing a first tunnel barrier layer on the first ferromagnetic free layer;
depositing a second ferromagnetic free layer on the first tunnel barrier layer;
depositing a second tunnel barrier layer on the second ferromagnetic free layer;
depositing a reference layer on the second tunnel barrier layer;
depositing a spacer layer on the reference layer;
depositing a buffer layer on the spacer layer;
depositing a pinned layer on the buffer layer;
forming a first patterned mask over the pinned layer; and
performing a first etching process to pattern the pinned layer, the buffer layer, the spacer layer, the reference layer, the second tunnel barrier layer, the second ferromagnetic free layer, the first tunnel barrier layer and the first ferromagnetic free layer to form a pattern by using the first patterned mask as an etch mask.
|