| CPC G11C 7/222 (2013.01) [G11C 7/109 (2013.01)] | 17 Claims |
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1. A semiconductor device, comprising:
an input/output interface circuit including:
a first data input/output pin;
a plurality of second data input/output pins;
a write clock signal pin configured to receive a write clock signal from a memory controller; and
a sampling circuit configured to generate sampling values by sampling a write training pattern included in write training data for write training using sampling write clock signals that correspond to last M toggling edges of the write clock signal toggling N times, and generate result values of the write training, where N is a natural number greater than M,
wherein the first data input/output pin is configured to receive the write training data from the memory controller during a write training operation, and
wherein the plurality of second data input/output pins are configured to output feed the result values of the write training generated based on the write clock signal and the write training data, to the memory controller.
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